1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device in general, and in particular, to a method for fabricating a flash memory device having a tunnel oxide layer with improved characteristics.
2. Description of the Prior Art
Generally, a flash memory device is one of the types of nonvolatile semiconductor memory devices. The flash memory device combines advantages of an erasable programmable read-only memory (EPROM) device with the advantages of an electrically erasable programmable read-only memory (EEPROM) device.
Such a flash memory device can realize a storage state of one bit by means of one transistor, and perform electrical programming and erasing. The flash memory device having the above characteristics includes a thin tunnel oxide layer formed on a silicon substrate, and a floating gate and a control gate stacked in layers between which an insulating layer is interposed.
However, as the flash memory device is reduced in size, the need for a tungsten gate electrode with low resistance is increased in the art. The use of tungsten for the gate electrode has the drawback that tungsten exposed to an oxidation process shows a rapid oxidizing reaction causing explosion (?)/enlargement(?) of the circuit pattern. In order to prevent such abnormal oxidation of tungsten, a sealing nitride layer should be additionally formed as a means of anti-oxidation, or selective oxidation should be performed only to the underlying polysilicon except tungsten.
In relation to the above, a conventional method for fabricating a flash memory device is described hereinafter with reference to FIGS. 1 to 3.
Referring to FIG. 1, on a cell region (A) of a silicon substrate 1, a tunnel oxide layer 3a, a polysilicon layer 5 for a floating gate, an oxide-nitride-oxide (ONO) layer 7, a polysilicon layer 9 for a control gate, a tungsten or tungsten nitride layer 11, and a hard mask nitride layer 13 are deposited in sequence.
In addition, on a cell peripheral region (B), a low voltage or high voltage gate oxide layer 3b, the polysilicon layer 9 for the control gate, the tungsten or tungsten nitride layer 11, and a hard mask nitride layer 13 are formed simultaneously with those of the cell region (A).
Then, the above-mentioned layers are selectively patterned to form respectively gate patterns on the cell region (A) and the cell peripheral region (B) Here, etching progress in the cell region (A) is stopped at the ONO layer 7.
Thereafter, a first selective oxidation process is performed in order to relieve etching damage of the low voltage or high voltage gate oxide layer 3b on the cell peripheral region (B). As a result, a selective oxidized layer 9a is formed on a lateral side of the polysilicon layer 9 for the control gate.
Next, while the cell peripheral region (B) is covered with a photo resist pattern (not shown), the ONO layer 7 and the polysilicon layer 5 for the floating gate on the cell region (A) are selectively patterned.
Subsequently, in order to relieve etching damage of the tunnel oxide layer 3a, a second selective oxidation process is carried out. A second selective oxidized layer 9b is therefore formed on a lateral side of the polysilicon layer 5 for the floating gate.
Next, a sealing nitride layer 15 for anti-oxidation is deposited over an entire resultant structure. The sealing nitride layer 15 is then, as shown in FIG. 2, anisotropically etched all through the cell region (A) and the cell peripheral region (B). Thus, a sealing nitride pattern 15a for anti-oxidation is formed into a spacer shape.
Thereafter, as shown in FIG. 3, the cell peripheral region (B) is covered with a photo resist pattern (not shown) and the cell region (A) is subjected to selective etch. By selectively etching the polysilicon layer 5 for the floating gate and the ONO layer 7 to expose a surface of the tunnel oxide layer 3a, a polysilicon pattern 5a and an ONO pattern 7a are therefore formed with a predetermined shape.
Though it is not shown in the drawings, a source and a drain are then formed in a surface of the cell region (A) of the silicon substrate 1 by implanting ions such as boron or arsenic.
The flash memory device is completed after a thermal process, a spacer-forming process, and the like are performed.
The above-described conventional method has drawbacks as follows. In the conventional method, the selective oxidation process is performed twice. The first selective oxidation process is performed to relieve etching damage to the low voltage or high voltage gate oxide layer 3b on the cell peripheral region (B). Also, the second selective oxidation process is performed to relieve etching damage of the tunnel oxide layer 3 after the layers on the cell region (A) are selectively patterned using a gate pattern mask.
Since the conventional selective oxidation process is carried out in a hydrogen-rich atmosphere, supplied hydrogen gas is often transferred to the gate oxide layer or the tunnel oxide layer. Unfortunately, such transferred hydrogen gas is trapped in the oxide layer, thus producing a trap site.
That is, the influx of hydrogen causes the characteristics of the oxide layer to be affected very seriously in the nonvolatile devices such as flash memory devices.
It is therefore an object of the present invention to provide an improved method for fabricating a flash memory device having a tunnel oxide layer with excellent characteristics by performing only a single normal oxidation process during metal contact etching.
This and other objects are attained by a method for fabricating a flash memory device in accordance with the present invention. The method begins with the step of sequentially forming a tunnel oxide layer, a floating gate, an oxide-nitride-oxide (ONO) layer, a control gate, and a hard mask on a silicon substrate. The hard mask, the control gate, the ONO layer, and the floating gate are then sequentially patterned. Next, an insulating layer is formed on the entire resultant structure, and a contact hole is formed in the insulating layer in order to expose a portion of the silicon substrate. Thereafter, oxidation is performed on the entire resultant structure including the contact hole.
According to another aspect of the present invention, a method for fabricating a flash memory device begins with forming in sequence a tunnel oxide layer, a floating gate, an oxide-nitride-oxide (ONO) layer, a control gate, and a hard mask nitride layer on a silicon substrate. The hard mask nitride layer, the control gate, the ONO layer, and the floating gate are then patterned in sequence. Next, a sealing nitride layer is formed on a lateral side of the patterned structure. Also, in order to form a spacer, a first insulating layer is deposited on the entire resultant structure and then selectively patterned. Thereafter, second, third and fourth insulating layers are formed in sequence on the entire resultant structure including the spacer, and a photo resist pattern is then formed on the fourth insulating layer in order to define a metal contact area. Next, the fourth, third and second insulating layers are selectively patterned through the photo resist pattern, so that a contact hole is formed exposing a portion of the silicon substrate. Also, oxidation is performed on the entire resultant structure including the contact hole.